1. Field of the Invention
The present invention relates to a semiconductor memory device, such as a dynamic RAM (DRAM), or the like, and more particularly, to improvements in the pattern layout of main word lines in a sub word decoder section for supplying main word lines and driving sub word lines.
2. Description of the Related Art
In recent years, semiconductor memory devices, such as DRAMs, have been increasing continually in capacity. In accordance with this, the word lines and bit lines used for selecting memory cells are constituted by low-resistance metal wiring layers, and a hierarchical structure is adopted for the word lines. The most typical composition of a DRAM in recent years is one where the wiring layers formed on a silicon substrate comprise two conducting layers composed of polysilicon and two metal wiring layers composed of aluminium of an alloy thereof. The first metal wiring layer is used for main word lines arranged in rows, and the second metal wiring layer located above this first layer is used for bit lines, column selection signal lines, and the like, arranged perpendicularly to the direction of the rows.
With the use of a hierarchical structure for word lines, there are provided a main word decoder for selecting and driving main word lines, and sub word decoders for selecting and driving sub word lines to which these main word lines are connected and which are in turn connected to memory cells. The main word lines are constituted by the first metal wiring layer and the sub word lines are constituted by the polysilicon conducting layer located therebelow. The main word decoder is located in a position at one end of the memory cell area, whilst the sub word decoders are distributed within the memory cell area.
A sub word decoder selected from the plurality of sub word decoders connected to the selected main word line by means of a separate selection signal drives the sub word line located subordinately thereto. This hierarchical structure avoids the operation of providing a single long word line in a high-capacity memory cell area and driving all of the memory cells on that row by means of the long word line. By adopting a hierarchical structure, a main word line constituted by a first metal wiring layer having a low resistance is driven, the corresponding rows are selected in a short time, and the short sub word lines formed in the underlying polysilicon conducting layer are driven individually, thereby driving the actual memory cells. By driving only the sub word lines belonging to the selected memory cell, it is possible to eliminate unnecessary driving of word lines, which helps to reduce power consumption.
If the foregoing composition is adopted, main word lines constituted by the first metal wiring layer are arranged in rows and sub word decoder circuits are formed such that they overlap with these main word lines. The sub word decoder circuits are formed by using the second of the polysilicon conducting layers, which is more adjacent to the silicon substrate than the first metal wiring layer. Furthermore, the sub word lines are constituted by using the polysilicon conducting layer. The layout efficiency is raised by using these sub word lines as gate electrodes for the memory cell selection transistors.
With the conventional multiple layer wiring structure and the hierarchical structure of word lines described above, it is necessary to lay out the sub word decoder circuits distributed within the memory cell area in a compact fashion. Since it is necessary to form a large number of sub word decoder circuits when a hierarchical word line structure is adopted, optimizing the layout of the respective sub word decoder circuits and minimizing the surface area thereof means being able to broaden the memory cell area, accordingly.
However, by forming the first metal wiring layer constituting the main word lines as a layer above the sub word decoder circuits, a trade off is generated between compactification of the sub word decoder circuits and reduction in the resistance of the first metal wiring layer constituting the main word lines. In other words, desirably, the main word lines constituted by the first metal conducting layer should be located at a small pitch corresponding to the pitch of the memory cells, whilst at the same time their resistance is reduced by forming the lines to a large width. On the other hand, it is also desirable for the sub word decoder circuits to be reduced in size. However, it is necessary to use a portion of the first metal conducting layer constituting the main word lines for the composition of the sub word decoder circuits, in the sub word decoder region. For example, in order to connect the polysilicon conducting layer with a region in the silicon substrate which contains an impurity of a different conductor type, it is not possible to connect the polysilicon conducting layer directly to the silicon substrate, but rather it is necessary first to connect the first metal conducting layer to the silicon substrate, and then to connect the polysilicon conducting layer thereto via the metal conducting layer. Alternatively, in order to connect the silicon substrate to the second metal conducting layer forming the bit lines, which occupies a position further above the substrate, the silicon substrate is first connected to the first metal conducting layer, which occupies a lower position, and then this lower first metal conducting layer is connected to the upper second metal conducting layer.
In this way, when forming the sub word decoder circuits, it is not possible to use all of the lower-positioned first metal conducting layer in this region for the main word lines, and in a portion of this region, it is necessary to provide patterns in the first metal conducting layer which form nodes having a different electric potential from the main word lines. The presence of these patterns in a portion of the metal conducting layer has some effect on the line width and linearity of the main word lines passing through this region. Depending on the layout, the pattern of the main word lines in the sub word decoder region may take a shape that is severely contorted, rather than a linear shape. Furthermore, due to the presence of the patterns in a portion of the metal conducting layer, a situation arises where the line width of the pattern of the main word lines cannot be further reduced.
Main word lines having a pattern shape of this kind cause resistance to increase, and lead to corruption or delaying of the signal waveform carried thereby. Delay or waveform corruption in the main word lines is not desirable in a hierarchical word line structure. This is because if the main word lines themselves has a low resistance, and they cannot be driven in a short period of time, then the merits of structuring the word lines hierarchically is lost. Moreover, if a portion of the main word lines becomes narrow, then this may lead to the occurrence of electromigration. Moreover, if a contorted pattern shape is adopted, it becomes necessary to increase the size of the sub word decoder region itself.